In recent years, for further improvement in the performance of semiconductor devices such as speeding up and an increase in the capacity, research and development is in progress to improve the performance by a three-dimensional integrated circuit having at least two layers of semiconductor device chips laminated to constitute a three-dimensional (3D) lamination, in addition to refinement of transistors and wiring.
A three-dimensional integrated circuit has a structure such that semiconductor device chips are connected e.g. by electric signal terminals such as solder bumps and are bonded by a filling interlayer formed by being filled with an interlayer filler composition.
Specifically, such a process is proposed (Non-Patent Document 1) that a thin film of an interlayer filler composition is formed on a wafer by coating, B-stage formation is carried out, and then chips are cut out by dicing, temporary bonding by pressure heating is repeatedly carried out by using the chips, and finally main bonding (solder bonding) is carried out under pressure heating conditions.
For practical use of such a three-dimensional integrated circuit device, various problems have been pointed out, and one of them is a problem of dissipation of heat generated from a device such as a transistor or wiring. This problem results from a commonly very low coefficient of thermal conductivity of an interlayer filler composition to be used for lamination of semiconductor device chips as compared with metals and ceramics, and there are concerns about a decrease in the performance due to accumulation of heat in laminated device chips.
As one means to solve the problem, an increase in the coefficient of thermal conductivity of the interlayer filler composition may be mentioned. For example, a highly thermally conductive epoxy resin is used as a resin itself constituting the interlayer filler composition, or such a resin is combined with a highly thermally conductive inorganic filler, to make the interlayer filler composition be highly thermally conductive. For example, Patent Document 1 discloses an interlayer filler composition having spherical boron nitride aggregates blended as a filler. Boron nitride is usually in the form of plate particles, and has different coefficient of thermal conductivity as between in the long axis direction and in the minor axis direction, however, by binding the boron nitride particles with a binder to form spherical aggregates, the coefficient of thermal conductivity becomes uniform in the respective directions, whereby the coefficient of thermal conductivity will be improved by blending the boron nitride aggregates as a filler in the resin.
Further, as a patent relating to the improvement in the thermal conductivity of an epoxy resin itself, a method of introducing a mesogen skeleton into an epoxy resin has been disclosed. For example, Non-Patent Document 2 discloses improvement in the thermal conductivity of an epoxy resin by introducing various mesogen skeletons. However, although improvement in the thermal conductivity is confirmed, such an invention cannot be said to be practical considering the balance of the cost, the process compatibility, the hydrolysis resistance and the thermal stability.
Further, Patent Document 2 discloses an epoxy resin having good thermal conductivity using only a biphenyl skeleton, but only very low molecular weight epoxy resins have been synthesized, which lack film forming properties, and such resins are hardly useful as a thin film.
Further, with respect to an epoxy resin composition containing an inorganic filler, a resin may be peeled on the inorganic filler surface, and a desired coefficient of thermal conductivity is not achieved in some cases. Further, an epoxy resin having a mesogen skeleton with a not high epoxy equivalent has high crystallinity and has a hard structure in many cases after being cured, and the balance between the thermal conductivity and reduction in the stress has been desired.
On the other hand, in a conventional process of mounting semiconductor device chip on an interposer or the like, first, electric signal terminals such as solder bumps on the semiconductor device chip side are subjected to activation treatment by a flux, and then bonded to a substrate having lands (electric connection electrode), and the space between the substrates is filled with a liquid resin or an underfill material having an inorganic filler added to a liquid resin, which is cured, whereby the bonding is completed. On that occasion, the flux is required to have properties to remove the surface oxide film on the metal electric signal terminals such as solder bumps and the lands, and to improve wettability, and further, an activation treatment function such as prevention of reoxidation on the metal terminal surface.
As the flux, commonly, in addition to an inorganic metal salt containing halogen excellent in capability in solving the metal oxide film of the electric signal terminals, an organic acid or an organic acid salt, an organic halogen compound or an amine, rosin or its constituent, is used alone or in combination of two or more of them (for example, Non-Patent Document 3).
Further, in the 3D lamination process of semiconductor device chips, if activation treatment of the electric signal terminals such as solder bumps using a flux is carried out first, a flux layer having low thermal conductivity is formed on the surface of the terminals, and there are concerns about inhibition of thermal conductivity between the laminated substrates by the interlayer filler composition, or deterioration by corrosion of connection terminals by remaining flux components. Accordingly, a flux which can be directly mixed with an interlayer filler composition having high thermal conductivity and which is less likely to corrode metal terminals has been desired.
As mentioned above, a highly thermally conductive interlayer filler composition has been required to have not only compatibility to the 3D lamination process and capability in being formed into a thin film, but also connection properties to electric signal terminals between semiconductor device chips, and further technical development has been required.